A MOSFET using silicon carbide (SiC) is used as a power semiconductor device. JP-A-2012-253293 discloses an example of a structure of the MOSFET using SiC. FIG. 4A schematically illustrates a structure from a gate structure to a source electrode in the semiconductor device (MOSFET). In the semiconductor device 80, a semiconductor substrate 90 made of SiC and having an n-type layer 91 formed on a surface thereof is used. A p-type diffusion layer 92 is locally formed in the n-type layer 91. In the p-type diffusion layer 92, an n+-type diffusion layer 93 of an n-type having a carrier concentration higher than the n-type layer 91 is formed. In the n+-type diffusion layer 93, an n++-type diffusion layer (a high concentration impurity layer) 94 of an n-type having a carrier concentration higher than the n+-type diffusion layer 93 is formed. The n-type layer 91 is formed on an epitaxial substrate (not shown) by an epitaxial growth. The p-type diffusion layer 92, the n+-type diffusion layer 93 and the n++-type diffusion layer 94 are respectively formed by a heat treatment after ion implantations. The n-type layer 91 becomes a drain region of the MOSFET and the n+-type diffusion layer 93 becomes a source region of the MOSFET.
A gate oxide film 81 is formed to cover the p-type diffusion layer 92 between the n-type layer 91 and the n+-type diffusion layer 93 on the surface of the semiconductor substrate 90. A gate electrode 82 made of polycrystalline silicon, which is highly doped to be conductive, is formed on the gate oxide film 81. By a voltage applied to the gate electrode 82, a channel is induced on a surface of the p-type diffusion layer 92 between the drain region (the n-type layer 91 of the surface) and the source region (the n+-type diffusion layer 93 of the surface) and a switching (on/off) of current is thereby controlled.
An interlayer insulation layer 83 is formed to cover the gate electrode 82 and a periphery thereof. The interlayer insulation layer 83 is opened on the n++-type diffusion layer 94 (the source region). In the opening, a silicide electrode 84 is formed on the n++-type diffusion layer 94. The silicide electrode 84 is formed of Ni silicide (NiSi, NiSi2 and the like), and a contact resistance between the silicide electrode 84 and the n++-type diffusion layer 94 is low. The contact resistance can be lowered. To this end, phosphorous (P) becoming a donor in SiC is doped in a large amount in the n++-type diffusion layer 94. A source electrode 85 is formed to cover an entire surface of the structure. In particular, when an impurity concentration of the n++-type diffusion layer 94 is high, it is possible to make a resistance between the source region (the n+-type diffusion layer 93 of the surface) and the source electrode 85 small.
Meanwhile, FIG. 4A shows that the source electrode 85 is formed over the entire surface. Actually, however, a patterning is made on the surface of the semiconductor substrate 90 so that the source electrode 85 and the gate electrode 82 are separated and leaded out. Also, although a drain electrode is not shown in FIG. 4A, the drain electrode is also appropriately leaded out from the surface or backside of the semiconductor substrate 90. The interlayer insulation layer 83 is also appropriately patterned in correspondence to the source and drain electrodes.
FIG. 4B is a sectional view illustrating a structure just after the gate electrode 82 is patterned when manufacturing the semiconductor device 80. The structure of FIG. 4A is formed by performing a process (1) of opening an upper side of the n++-type diffusion layer 94 after forming the interlayer insulation layer 83 on the entire surface, a process (2) of forming the silicide electrode 84 in the opening, a process (3) of forming the source electrode 85 and the like for the structure of FIG. 4B. Although both the gate oxide film 81 and the interlayer insulation layer 83 have SiO2 as a main component, the gate oxide film 81 is formed to be thin by thermal oxidation and the interlayer insulation layer 83 is formed to be thicker than the gate oxide film 81 by a CVD method and the like.
When manufacturing a MOSFET of Si, a gate oxide film is formed on a semiconductor substrate by thermal oxidation, a gate electrode thereon is patterned and then a diffusion layer (the n+-type diffusion layer 93) becoming a source region is formed. However, when manufacturing the MOSFET of SiC, since a temperature of the heat treatment for forming the diffusion layer is very high, it is difficult to form the gate oxide film and the like before forming the diffusion layer. For this reason, in order to manufacture the structure of FIG. 4B, the process of forming the gate oxide film 81 is performed after forming the p-type diffusion layer 92, the n+-type diffusion layer 93 and the n++-type diffusion layer 94 in the semiconductor substrate 90 having the n-type layer 91.